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CHAPTER 8 NOTES ON TARGET SYSTEMS
This chapter explains the basic notes on the target system for rewriting the flash memory in the microcontroller
using the PG-FP4.
CPU Pin
RESET
Design Proposal
Do not connect the RESET signal generator on the target system to the RESET signal of the PG-FP4.
Otherwise, a signal conflict will occur. To avoid the conflict, isolate the RESET signal generator from the RESET
signal of the PG-FP4.
Do not generate RESET while the PG-FP4 is connected. This must be especially noted in a system that uses
an external watchdog timer.
Connect the RESET signal of the PG-FP4 at a point where the status of the programmer RESET signal and that
of the CPU RESET pin are the same.
Correct connection:
CPU
PG-FP4 RESET
RESET
Avoid the following RESET signal connection.
? Connection to a point where the target CPU RESET rise time is slower than the PG-FP4 RESET rise time.
Incorrect connection:
CPU
PG-FP4 RESET
OC
RESET
It takes time for the CPU RESET pin to go high after the PG-FP4 RESET level goes from low to high.
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User ’s Manual U15260EJ4V0UM
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